1. Field of the Invention
The present invention relates to a back bias voltage level sensing circuit, and more particularly, to a back bias voltage level sensing circuit which is capable of preventing a malfunction caused due to a switching current, by turning on a back bias voltage level sensing unit after the switching current, that occurs when a circuit is driven or stopped, is flown to a ground.
2. Description of the Background Art
FIG. 1 is a circuit diagram of a back bias voltage level sensing circuit in accordance with a conventional art, in which a back bias voltage level sensing unit is turned on once in every predetermined period to sense a back bias voltage level.
As shown in this drawing, the back bias voltage level sensing circuit includes a constant current generation unit 1 for generating a constant current ICON regardless of a variation of a power supply voltage VCC; a switch 2 for transferring or disconnecting the constant current ICON generated from the constant current generation unit 1 under the control of a switch control signal DETSW; a current distribution unit 3 for distributing the constant current ICON transferred by the switch 2 by using a current mirror; a back bias voltage level sensor 4 for sensing a level of a back bias voltage VBB by means of the current distributed by the current distribution unit 3 and outputting a sensing signal DETA; and a switching controlling unit 5 for receiving an oscillating signal OSC and the sensing signal DETA from the back bias voltage level sensing unit 4 and outputting a switch control signal DETSW for turning on and turning off a switch in a predetermined period.
The constant current generation unit 1 includes a first PMOS transistor PM1 being connected in series between a power supply voltage VCC and a ground voltage VSS, having a gate connected to the ground voltage VSS; a first NMOS transistor NM1 having a gate and a drain which are commonly connected; a second PMOS transistor PM2 connected in series between the power supply voltage VCC and the ground voltage VSS, having a gate and a drain which are commonly connected; a second NMOS transistor having a gate connected to the gate of the first NMOS transistor NM1; and a third PMOS transistor PM3 having a source to which the power supply voltage is applied, a gate connected to the gate of the second PMOS transistor PM2, and a drain to which the constant current flows.
The switch 2 includes a fourth PMOS transistor PM4 having a gate to which a switch control signal DETSW inverted by a first inverter INV1 is applied, a source to which the constant current ICON from the constant current generation unit 1 is applied, and a drain connected to a first node N1.
The current distribution unit 3 includes a fifth and sixth PMOS transistors being connected in series between the first node N1 and the ground voltage VSS, each having a gate connected to the ground voltage VSS; a seventh and eighth PMOS transistors PM7 and PM8 being connected in series between the first node N1 and a sensing node NS, each having a gate connected to the ground voltage VSS; and a third NMOS transistor NM3 having a gate connected to the ground voltage VSS and a drain connected to the sensing node NS so as to sense a level of the back bias voltage VBB applied to a source thereof.
The back bias voltage level sensor 4 includes a second and a third inverter INV2 and INV3 for sequentially inverting a level of the sensing node NS; a first NAND gate ND1 having a first input terminal to which an output signal from the third inverter INV3 is applied, and a second input terminal to which the switch control signal DETSW is applied; and a fourth inverter INV4 for inverting the output signal from the NAND gate ND1 and outputting a sensing signal DETA.
The switching controlling unit 5 includes a first NOR gate NOR1 having a first input terminal to which the sensing signal DETA is applied, and a second input terminal to which the oscillating signal OSC is applied; and a fifth inverter INV5 for inverting the output signal from the first NOR gate NOR1 and outputting the switch control signal DETSW.
The operation of the back bias voltage level sensing circuit of the conventional art constructed as described above will now be explained.
A gate voltage of the first NMOS transistor NM1 is constantly maintained by the general constant voltage generating circuit having the first PMOS transistor PM1 and the first NMOS transistor NM1, regardless of a variation of the power supply voltage VCC.
As to the constant current generating circuit having the second PMOS transistor PM2 and the second NMOS transistor NM2, since the first and second NMOS transistors NM1 and NM2 have the commonly connected gate, having the same voltage, the voltage difference VGS between the gate and the source of the second NMOS transistor NM2 is constantly maintained. Accordingly, a constant current is generated regardless of a variation in the power supply voltage VCC. Also, since the voltage difference VGS between the gate and the source of the second PMOS transistor PM2 is constantly maintained, a voltage difference between the power supply voltage VCC and the gate voltage of the second PMOS transistor PM2, so that a constant current ICON is generated through the third PMOS transistor PM3.
The constant current ICON of the constant current generation unit 1 is transferred or disconnected in a predetermined period by the switch 2 which is controlled by the switch control signal DETSW.
The constant current ICON transferred by the switch 2 is distributed to a first distribution current ID1 and a second distribution current 1D2 by the current distribution unit 3. The distribution rate is determined by the length and the width of each channel of the fifth, sixth, seventh and eighth PMOS transistors.
A reference level VREF of the back bias voltage VBB to be sensed is determined by the voltage difference VGS between the gate and the source of the third NMOS transistor NM3 at the time when the second distribution current ID2, distributed over the constant current ICON through the third NMOS transistor NM3, flows thereto, and at this time, the voltage level of the sensing node NS is set by a logic threshold voltage VTH of the second inverter INV2.
When the switch 2 is turned on, if the level of an applied back bias voltage VBB is higher than the reference level VREF, the level of the sensing node NS becomes higher than the threshold voltage VTH of the second inverter INV2, so that the output signal from the second inverter INV2 becomes a low level and the sensing signal DETA is changed to a high level. Accordingly, the switch control signal DETSW becomes a high level regardless of the oscillating signal OSC to keep the switch 2 being turned on. At this time, the back bias voltage pumping circuit (not shown) is driven, rendering the back bias voltage level to be gradually lowered down.
Reversely, when the level of an applied back bias voltage is lower than the reference level VREF, the level of the sensing node NS becomes lower than the threshold voltage VTH of the second inverter INV2 and the sensing signal DETA becomes a low level so as to stop the pumping operation of the back bias voltage pumping circuit (not shown), and the switch control signal DETSW become a low level to turn off the switch 2.
In this respect, whether or not the switch 2 is turned on or turned off is determined by the oscillating signal OSC. Thus, when the switch control signal DETSW becomes a low level as the oscillating signal OSC becomes a low level as shown in FIG. 2A and FIG. 2B, the switch 2 is turned off to disconnect the constant current ICON and the level of the sensing node NS is the same as that of the back bias voltage VBB as shown in FIG. 2E.
Meanwhile, when the switch control signal DETSW is changed to a high level, and thus, the switch 2 is turned on, if the level of the back bias voltage VBB is lower than the reference level VREF, the level of the sensing node NS becomes lower than that of the threshold voltage VTH of the second inverter INV2. Then, the output signal from the second inverter INV2 becomes a high level and the sensing signal DETA becomes a low level, so that the back bias voltage pumping circuit (not shown) won't perform pumping operation.
However, though the strength of the second distribution current ID2 generated for sensing the level of the back bias voltage and distributed over the constant current ICON by the current distribution unit 3 is merely a few micro ampere .mu.A, a few mili ampere mA of a switching peak current, that is generated when the third PMOS transistor PM3 of the switch 2 is turned on or turned off, flows. Thus, when the switch 2 is turned on, as shown in FIG. 2C, since the level of the sensing node NS is heightened by inflow of the switching peak current, even though the back bias voltage level is lower than the reference level VREF, as shown in FIG. 2D, the sensing signal DETA becomes a high level so as to drive the back bias voltage pumping circuit until the heightened level of the sensing node NS is dropped down to be lower than the threshold voltage VTH of the second inverter INV2.
Accordingly, the back bias voltage level is lowered down, and the lowered back bias voltage level is applied to a substrate of a semiconductor memory device, rendering the threshold voltage of a MOS transistor to be increased, which causes problems in that the operational speed of the semiconductor memory device is delayed and the back bias voltage pumping circuit is malfunctioned, resulting in increasing a current consumption.